How sand is transformed into silicon chips

The amazing journey from sandcastle to Core i7 processor

Step six: Adding gates to complete the MOSFETs

With the n-type and p-type regions in place, all that is needed to complete the MOSFETs is the gate. As with many of these steps, the first job is to produce a patterned oxide layer as described in Step 4. In this case, the oxide layer will have gaps only in the gate regions of the MOSFETs. Again, there are different ways of making the gates, but the method described here is typical.

As shown in the diagram in the 'Understanding MOSFETs' box, the first part of the gate is a very thin insulating layer of silicon dioxide, deposited on the surface of the silicon between the source and the drain. This is done using chemical vapour deposition (CVD), a process that takes place in a furnace filled with various gases that cause a chemical reaction to take place on the surface of the silicon.

To complete the MOSFET, a layer of silicon is applied over the top of the thin oxide layer to act as a conductor. Again, CVD is used, and the silicon is applied via an oxidation reaction in which gaseous silicon hydride reacts with oxygen to give silicon and water as products.

Step seven: Connecting the MOSFETs with copper tracks

Once all of this has been done, the wafer will contain billions of MOSFETs. In order for them to work together as circuits, they need to be connected together to produce lots of individual chips, each of them still containing millions of MOSFETs. The process used by Intel is as follows:

(A) The initial state of the MOSFETs on the wafer.

(B) Before the addition of copper circuitry can be carried out, a layer of insulation has to be applied to the wafer so that the interconnecting tracks don't short all the MOSFETs. Silicon dioxide is used as the insulator, and this layer is built up on the surface of the wafer either by oxidising it in a furnace or by a process of chemical vapour deposition.

With the entire surface of the wafer covered in an insulating layer of silicon dioxide, it's no longer possible to make connections to the source, drain and gate of the MOSFETs.

There are a number of ways of restoring connections, but for simplicity's sake we're going to describe an up-and-coming method called 'double damascene'. This method involves two damascene steps – one to create tungsten connecting pins and the second to make copper interconnects.

(C) Hydroflouric acid is used to etch holes in the silicon dioxide insulation (through a layer of photoresist).

(D) After that, trenches in the pattern of the required interconnection tracks are etched into the silicon dioxide through another photoresist layer.

(E) A top layer of copper is then applied by electroplating. This fills the trenches and holes to make contact with the underlying MOSFETs. The resultant metallic pins that protrude through the insulating layer are called 'vias'.

(F) The wafer is now covered in a layer of copper. The final stage is to take this off. In a process called chemical-mechanical polishing, the excess copper is removed so that the desired amount is left to form tracks in the trenches and holes.

FINAL STAGES: An insulating layer of silicon dioxide protects the MOSFETs. Holes etched through it permit connections to be made

Step eight: Completing the circuit

It's not always feasible to wire up a circuit without wires crossing. If there was just one rogue interconnection, any tracks that crossed would short. To avoid this, MOSFETs have more than one metallic layer, each insulated by another layer of silicon dioxide and connected using vias.

Step nine: Sorting the good chips from the bad

All being well, the wafer should now contain a couple of hundred dies (the official name for chips), but in reality, not all of them will work correctly. Semiconductor manufacturers tend not to publish these figures, but industry experts consider a typical yield (the percentage of working dies on a wafer) to be about 60 per cent.

The next job is therefore to find out which dies are working, a task that is carried out by a wafer probe. This piece of hardware uses pins that line up with the contacts on a die, through which electrical signals can be passed to put the processor through its paces.

To sort the wheat from the chaff, dies are categorised as 'functional' or 'non-functional', but there might also be several examples of partially functional dies. Processors in which only some of the dies are working can still be sold as a lower-specification product. After all of the dies have been tested, the wafer is sawn up into individual dies that are sorted and deployed according to the results of the wafer test.

Step ten: Packaging to survive the real world

We might have a fully working die now, but, as it stands, it's much too fragile to ship to a motherboard manufacturer. Furthermore, the die has hundreds or thousands of connections to the outside world, but it's only a few millimetres square, making it far too fiddly for an electronics company to make connectors for it.

The final step, therefore, is to encase the bare chip into a package that most people would think of as a 'processor'. Several methods are available for this process. Whichever one is used, the end result is that the die is firmly attached to the package, and electrical connections are made between the contacts on the die and the contacts on the package.

A final test on the finished assembly is all that's needed before the processor can be shipped to a manufacturer and ultimately used to power a computer.


First published in PC Plus Issue 281