Intel's parallel processing vision

Power consumption issues have led Intel into developing multi-core CPUs like Nehalem

With multi-core processors now established, what are Intel’s plans are for pushing the full potential of parallelism in computing? At the IDF in Shanghai, we caught up with Intel’s vice president and director of research,

Andrew Chien

, in an effort to find out.

Prior to joining Intel, Andrew Chien spent 15 years in the academic community working on various aspects of hardware and software for parallelism. Chien now leads many of Intel’s external efforts for research.

TechRadar: Will true parallel computing require a rethink, overhaul or a complete replacement of the current x86 CPU architecture that today's PCs are based on?

Andrew Chien: It’s safe to say that x86 is really deeply rooted in a whole range of software compatibility and toolchain aspects, which is the glue that binds the industry. When you look at parallelism, there are some issues in how you get things together and a whole new dimension of challenges.

We fully expect, because we’re Intel, that a full range of parallel systems will be built based on x86 or extensions of x86, and they’ll work just fine.

TechRadar: Have inherent difficulties materialised in the 30 years that x86 has been around?

Andrew Chien: Oh totally – but every instruction set architecture evolves from the time it’s introduced, and Intel has continuously been adding improvements to the architecture. After all, it started as an 8-bit architecture, right?

While most of the academic world has focussed on this RISC [reduced instruction set computer] versus CISC [complex instruction set computer] competition. In some parts of the academic community there is a deeply held belief that RISC won.

But the interesting thing is moving into [an age] where you’re frequency limited on the processor due to power. We’re seeing that now and Intel has changed its strategy. There’s now a lot of innovation around being more efficient from a power point of view with the instruction set.

So a lot of the extensions and the enhancements that you’re seeing coming out of Intel right now are really about that ability to describe a whole bunch of computation, with really more complex instructions. This allows you to achieve higher power efficiency.

TechRadar: Is this efficiency of power and the limitations on clock speeds also pushing forward the multi-core aspect?

Andrew Chien: Absolutely.

TechRadar: But beyond multi-core, will we also see a lot of operations pushed off the CPU and into the GPU or other discrete media processing hardware?

Andrew Chien: I think it certainly pushes modifications to the architecture extensions and so on that could increase power efficiency or single thread efficiency in a single stream.

The power offload is also a fundamental driver behind parallelism using multiple cores because it’s been known for at least 30 years that if you go parallel (and you don’t scale the clock as fast), you can get more operations per second, per Watt. It’s always just been so hard to go parallel as people haven’t wanted to go down that path.

This desire to offload stuff to special purpose engines was first seen with special engines for cryptography. There are also some media engines in small mobile devices, like a voice recorder. They have custom ASICs or custom designs bred to do the media encoding and decoding. Some of [this approach] is down to cost, but also some of that is because a hardwired design is more power-efficient compared to a general purpose core.

I wouldn’t really hold up GPUs as being any more power efficient. But I think there is a spectrum of general purpose designs, all the way down to hardwired implementations for power efficiency, which Intel is very conscious of. We look at integrating things into our SOCs [System On a Chip] and other kinds of products like that to address those markets.