The deserts of Arizona are home to Intel's Fab 32, a $3billion factory that's performing one of the most complicated electrical engineering feats of our time.

It's here that processors with components measuring just 45 millionths of a millimetre across are manufactured, ready to be shipped out to motherboard manufacturers all over the world.

Creating these complicated miniature systems is impressive enough, but it's not the processors' diminutive size that's the most startling or impressive part of the process.

It may seem an impossible transformation, but these fiendishly complex components are made from nothing more glamorous than sand. Such a transformative feat isn't simple. The production process requires more than 300 individual steps.

We've taken an in-depth look at Intel's manufacturing method and distilled the whole process into 10 stages. So, to find out how sandcastles become Core i7 processors, read on – and prepare to be amazed.

Step one: Converting sand to silicon

Sand is composed of silica (also known as silicon dioxide), and is the starting point for making a processor. Sand used in the building industry is often yellow, orange or red due to impurities, but the type chosen in the manufacture of silicon is a purer form known as silica sand, which is usually recovered by quarrying.

To extract the element silicon from the silica, it must be reduced (in other words, have the oxygen removed from it). This is accomplished by heating a mixture of silica and carbon in an electric arc furnace to a temperature in excess of 2,000°C.

The carbon reacts with the oxygen in the molten silica to produce carbon dioxide (a by-product) and silicon, which settles in the bottom of the furnace. The remaining silicon is then treated with oxygen to reduce any calcium and aluminium impurities. The end result of this process is a substance referred to as metallurgical-grade silicon, which is up to 99 per cent pure.

This is not nearly pure enough for semiconductor manufacture, however, so the next job is to refine the metallurgical-grade silicon further. The silicon is ground to a fine powder and reacted with gaseous hydrogen chloride in a fluidised bed reactor at 300°C to give a liquid compound of silicon called trichlorosilane.

Impurities such as iron, aluminium, boron and phosphorous also react to give their chlorides, which are then removed by fractional distillation. The purified trichlorosilane is vaporised and reacted with hydrogen gas at 1,100°C so that the elemental silicon is retrieved.

During the reaction, silicon is deposited on the surface of an electrically heated ultra-pure silicon rod to produce a silicon ingot. The end result is referred to as electronic-grade silicon, and has a purity of 99.999999 per cent.

Step two: Creating a cylindrical crystal

Although pure to a very high degree, raw electronic-grade silicon has a polycrystalline structure. In other words, it's made up of lots of small silicon crystals, with defects called grain boundaries between them. Because these anomalies affect local electronic behaviour, polycrystalline silicon is unsuitable for semiconductor manufacturing.

To turn it into a usable material, the silicon must be turned into single crystals that have a regular atomic structure. This transformation is achieved through the Czochralski Process. Electronic-grade silicon is melted in a rotating quartz crucible and held at just above its melting point of 1,414°C.

A tiny crystal of silicon is then dipped into the molten silicon and slowly withdrawn while being continuously rotated in the opposite direction to the rotation of the crucible. The crystal acts as a seed, causing silicon from the crucible to crystallise around it. This builds up a rod – called a boule – that comprises a single silicon crystal.

The diameter of the boule depends on the temperature in the crucible, the rate at which the crystal is 'pulled' (which is measured in millimetres per hour) and the speed of rotation. A typical boule measures 300mm in diameter.

Step three: Slicing the crystal into wafers

Integrated circuits are approximately linear, which is to say that they're formed on the surface of the silicon. To maximise the surface area of silicon available for making chips, the boule is sliced up into discs called wafers.

The wafers are just thick enough to allow them to be handled safely during semiconductor fabrication. 300mm wafers are typically 0.775mm thick. Sawing is carried out using a wire saw that cuts multiple slices simultaneously, in the same way that some kitchen gadgets cut an egg into several slices in a single operation.

Silicon saws differ from these kitchen tools in that the wire is constantly moving and also carries with it a slurry of silicon carbide, the same abrasive material that forms the surface of 'wet-dry' sandpaper. The sharp edges of each wafer are then smoothed down to prevent the wafers from chipping during later processes.

Next, in a procedure called 'lapping', the surfaces are polished using an abrasive slurry until the wafers are flat to within an astonishing 2μm (two thousandths of a millimetre). The wafer is then etched in a mixture of nitric, hydrofluoric and acetic acids.

The nitric acid oxides the surfaces to give a thin layer of silicon dioxide – which the hydrofluoric acid immediately dissolves away to leave a clean silicon surface – and the acetic acid controls the reaction rate. The result of all this refining and treating is an even smoother and cleaner surface.

Step four: Making a patterned oxide layer

In many of the subsequent steps, the electrical properties of the wafer will be modified through exposure to ion beams, hot gasses and chemicals. But this needs to be done selectively to specific areas of the wafer in order to build up the circuit.

STAGE FOUR: A multistage process is used to create an oxide layer in the shape of the required circuit features

In some cases, this procedure can be achieved using 'photoresist', a photosensitive chemical not dissimilar to that used in making photographic film (just as described in steps B, C and D, below).

Where hot gasses are involved, however, the photoresist would be destroyed, making another, more complicated, method of masking the wafer necessary. To overcome the problem, a patterned oxide layer is applied to the wafer so that the hot gasses only reach the silicon in those areas where the oxide layer is missing. Applying the oxide layer mask to the wafer is a multistage process, as illustrated to the left.

(A) The wafer is heated to a high temperature in a furnace. The surface layer of silicon reacts with the oxygen present to create a layer of silicon dioxide.

(B) A layer of photoresist is applied. The wafer is spun in a vacuum so that the photoresist spreads out evenly over the surface before being baked dry.

(C) The wafer is exposed to ultraviolet light through a photographic mask or film. This mask defines the required pattern of circuit features. This process has to be carried out many times, once for each chip or rectangular cluster of chips on the wafer. The film is moved between each exposure using a machine called a 'stepper'.

(D) The next stage is to develop the latent circuit image. This process is carried out using an alkaline solution. During this process, those parts of the photoresist that were exposed to the ultraviolet soften in the solution and are washed away.

(E) The photoresist isn't sufficiently durable to withstand the hot gasses used in some steps, but it is able to withstand hydrofluoric acid, which is now used to dissolve those parts of the silicon oxide layer where the photoresist has been washed away.

(F) Finally, a solvent is used to remove the remaining photoresist, leaving a patterned oxide layer in the shape of the required circuit features.

Step five: Creating n-type and p-type regions

The fundamental building block of a processor is a type of transistor called a MOSFET – you can see how they work below. The type of device illustrated there is a 'p-channel' MOSFET (so-called because it uses p-type material). Processors also use 'n-channel' MOSFETs, which use n-type material.

MOSFET DESIGN: MOSFETs are the switches at the heart of processor design

The first step in creating a circuit is to create n-type and p-type regions. Below is the method Intel uses for its 90nm process and beyond:

(A) The wafer is exposed to a beam of boron ions. These implant themselves into the silicon through the gaps in a layer of photoresist to create areas called 'p-wells'. These are, confusingly enough, used in the n-channel MOSFETs.

A boron ion is a boron atom that has had an electron removed, thereby giving it a positive charge. This charge allows the ions to be accelerated electrostatically in much the same way that electrons are accelerated towards the front of a CRT television, giving them enough energy to become implanted into the silicon.

(B) A different photoresist pattern is now applied, and a beam of phosphorous ions is used in the same way to create 'n-wells' for the p-channel MOSFETs.

(C) In the final ion implantation stage, following the application of yet another photoresist, another beam of phosphorous ions is used to create the n-type regions in the p-wells that will act as the source and drain of the n-channel MOSFETs.

This has to be carried out separately from the creation of the n-wells because it needs a greater concentration of phosphorous ions to create n-type regions in p-type silicon than it takes to create n-type regions in pure, un-doped silicon.

(D) Next, following the deposition of a patterned oxide layer (because, once again, the photoresist would be destroyed by the hot gas used here), a layer of silicon-germanium doped with boron (which is a p-type material) is applied.

MOSFET CREATION: The properties of the silicon are modified to produce n-type and p-type regions