And what about what's on the outside of each block?
BBs are separated by groups of metallic wires. These wires are connected to each other and to all inputs and outputs of the adjacent BBs by microswitches. The same burning file already mentioned also lists which micro-switches must be opened to let electricity flow. By opening different microswitches and properly configuring the BBs, you implement different circuit diagrams. This is what constitutes the field programmability of FPGAs.
You said 'within reasonable limits' a bit ago. That sounds a little suspicious…
Basically, the only limits are space and speed. The number of BBs inside each FPGA is constant, and physically limited by the size of the die. If the FPGA on your desk contains one BB less than what your design requires, you're out of luck: buy a bigger FPGA, or start the design from scratch.
Another space-related limit is finding the right combination of open micro-switches to implement all the internal 'wires' that are needed to connect all the BBs. It can, and does happen, that there are enough BBs but no free paths to realise all the needed wires among them. Equally frequent is the case where a route between two blocks exists, but it is so long that signals can't travel on it at the desired speed. In that case, you must try a different routing. The last, intrinsic limit is silicon speed. Each BB has a minimum internal delay, and you can't use a clock whose period is less than that delay.
How are FPGAs used in the industry?
In two ways, mainly. The first is as prototypes. An ASIC is terribly expensive to make, so it is common practice to buy a few FPGAs, mount them on a board, test the design with them and put it into an ASIC only when everybody is absolutely certain that it is correct. The second case is when you are sure of the design, but need so little units that it would be unprofitable to make a custom ASIC mask.
If FPGAs are so flexible, how come that they haven't completely replaced application-specific integrated circuits?
Because there is a price to pay. Fully customised masks mean that ASICs are optimised much more than FPGAs: the ASIC version of a given circuit requires much less space than in an FPGA and it also goes much faster, dissipates much less power and, when needed in large volumes, yields a much lower unit price. This is why, for example, you're unlikely to find FPGAs in your phone or iPod in the foreseeable future.
How do you go about designing an FPGA?
There are four main phases: the actual design, then simulation, logical synthesis, layout and burning. The last step consists of downloading the result of the layout into the flash memory connected to the FPGA. Design and simulation are done, as with ASICS, with HDL languages.
I seem to remember HDLs. Would you remind me what logical synthesis is?
This would be the moment when the final behavioural circuit model written in some HDL language is translated, by special compilers, to one huge Carnot map of the whole thing, that is, to one long list of basic Boolean operators and connecting nets: this is why this map is usually called netlist.
Then comes the layout, you said.
Right. The layout is the process of looking at the netlist and figuring out how to configure each BB and which micro-switches must be open to implement exactly the required function at the required speed.
Back to design for one moment: can FPGAs be open source, like software?
