After selling off its MIPS processor business back in 2017, Imagination Technologies has focused on what it does best, namely graphics processing technologies. But CPUs seem to remain on the company’s radar as this week the firm announced its first RISC-V computer architecture course under-graduate teaching as part of its Imagination University Programme (IUP).
This does not necessarily bring Imagination back to CPU business right now as it yet has to announce any RISC-V products, but rather demonstrates the company’s interests.
The course is called “RVfpga: Understanding Computer Architecture” and it includes theoretical and practical materials to help students understand the basics of processor architecture in general as well as modification or RISC-V cores and microarchitectures. The base core that will be used for the course is Western Digital’s SweRV. The course was made in collaboration between Imagination Technologies, Sarah Harris and Daniel Chaver, two associate professors from RIOS Laboratory.
Architecture to watch
RISC-V is an open-source architecture that can be used by anyone to build actual processor cores and SoCs without paying any royalties to the developer of architectures. Meanwhile, nothing prevents IP companies to build commercial versions of RISC-V cores for their projects.
While traditionally Imagination has focused on graphics processing for mobile SoCs, in the recent years the company began to offer IP for AI and computer vision applications, including those for automotive markets. Building complete platforms for automotive, industrial, and other emerging verticals might require Imagination to offer its own CPU IP too (or at least use CPU cores designed by someone else) and RISC-V is an architecture to watch these days.
Officially, Imagination yet has to engage back into CPU cores business and it is unclear whether the company actually has such plans. But the RISC-V course as part of its IUP program showcases the direction where Imagination is looking at.
“RISC-V is real and will pervade every computing level in the next five years,” said Robert Owen, Director Worldwide University Programme, Imagination.
“Its openness has enabled designers at all levels to get involved with processors without having to worry about licensing at the early stages of design. This is empowering a new generation to experiment! Up to now, academic activity has been focused on SoC design. This course is the first to provide the all-important foundation of understanding of the components of the RISC-V “engine” and how they come together. I am delighted that the Imagination University Programme has led the creation of these materials.”
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Anton Shilov is the News Editor at AnandTech, Inc. For more than four years, he has been writing for magazines and websites such as AnandTech, TechRadar, Tom's Guide, Kit Guru, EE Times, Tech & Learning, EE Times Asia, Design & Reuse.