Major Arm licensee adopts royalty-free RISC-V core for next-gen processors

(Image credit: Andes Technology)

The RISC-V open-standard instruction set architecture (ISA) has become quite a phenomenon in the recent years as multiple companies that traditionally use Arm’s ISA or processor cores decided to join the emerging ecosystem. Renesas Electronics has now announced that it will use a 32-bit RISC-V core designed by Andes Technology for its upcoming application-specific standard products (ASSPs). 

Renesas’s pre-programmed ASSPs based on the AndesCore IP 32-bit RISC-V cores will come with specialized user interface tools to set application parameters and will eliminate the initial RISC-V development and software investment barrier for companies that have no experience with the ISA. This will greatly simplify deployment of such chips that will begin sampling in the second half of 2021.  

Renesas, one of the world’s largest supplier of chips and a major supplier of auto semiconductors, has used Arm technology extensively in its RZ, RA, and RE families for many years. Renesas also uses CISC cores in its RX-series microcontroller lineup (which it inherited from Hitachi and Mitsubishi) as well as NEC RISC cores in its RH controllers (inherited from NEC), but Arm has always been a technology of choice for the company. 

“The scalable range of performance, selectable safety features, and customization options provided by the Andes RISC-V core IP enables Renesas to provide innovative solutions for future application-specific standard products,” said Sailesh Chittipeddi, Executive Vice President, General Manager of Renesas’ IoT and Infrastructure Business Unit. “Customers looking for cost-effective alternative paths for existing or emerging applications will benefit from the reduced time to market and lower development costs.” 

Renesas does not disclose anything about its RISC-V-powered ASSPs, so it is impossible to make any judgements regarding the global impact of the announcement. But when a multi-billion-dollar Arm licensee decides to try RISC-V for a series of products, this is an important news by itself. It is also imperative that Andes Technology, a designer of custom processor cores, is working on multiple RISC-V cores. 

“Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA) for system-on-chips (SoC),” said Frankwell Lin, President of Andes Technology Corp. “Not only does this represent a milestone for Andes, but it marks the arrival of the open-source RISC-V ISA as a mainstream computing engine. Renesas customers will benefit from a modern ISA constructed for the needs of 21st century computing.”

Sources: RenesaseeNews Europe

Anton Shilov is the News Editor at AnandTech, Inc. For more than four years, he has been writing for magazines and websites such as AnandTech, TechRadar, Tom's Guide, Kit Guru, EE Times, Tech & Learning, EE Times Asia, Design & Reuse.