AMD outlined a new ambidextrous compute approach and architecture during its Core Innovation Update press conference in San Francisco today, revealing a number of announcements to go along with on this two-handed theme.
It also treated the gathered group to the first public demo of Seattle, it's first 64-bit ARM processor.
The company is stressing an ARM and x86 future, one where the pair of processor architectures dominate embedded, server, client and semi-custom markets. To this end, AMD announced it's now an ARM architectural licensee and is developing its own ARM cores.
"We set out a couple of years ago to ensure that as we continue to evolve our core markets, we also build the bridge to the future. And the bridge to the future is offering both ARM and x86 in our portfolio," Lisa Su, senior vice president and general manager of Global Business Units, said.
Bridge to the clouds
The chipmaker announced its Project SkyBridge ambidextrous design framework, a family of 20nm APUs and SoCs due in 2015. SkyBridge will mark the first time 64-bit ARM and x86 processors are pin compatible, Su said.
x86 SkyBridge products will utilize the "Puma+" cores first announced with the Beema and Mullins APUs, and will have full Heterogenous System Architecture (HSA) support. Graphics Core Next will find a place in the family as well. On the ARM end, low-power A57 64-bit ARM Cores will make the SkyBridge leap, and they'll mark AMD's first HSA Android platform.
Project SkyBridge products are intended for imbedded and client markets, Su said.
"It's an opportunity for us to help customers innovate, differentiate and also reduce their time to market," she concluded.
Going to Seattle and beyond
As for this year, AMD is hanging its hat on Seattle.
"We chose [a 64-bit ARM chip] because we believe there is a fundamental disruption in the server market over the next few years," Su said.
Seattle was treated to its first public demonstration during the press conference. Already announced, the 28nm 64-bit ARM server processor zipped through a web hosting demo onstage, easily handling generating a WordPress blog and playing video on the fly.
Seattle can pack up to 8 ARM Cortex A57 cores and up to 4MB shared L2 and 8MB L3 cache, Su described.
On the memory side, the city-named CPU can store up to 128GB per core and features dual channel DDR3/4 with ECC up to 1866MHz. Finally, Seattle is ARM Server Base System Architecture specification compliant.
As the company moves into 2016 and beyond, its overarching strategy - an ambidextrous one, mind you - centers on developing 64-bit ARM cores in conjunction with new 64-bit x86 cores. Vague, but we expect AMD to share more when it's got a little more practice using its other processing arm.